1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a memory cell provided with a storage portion comprised of films having a charge storing capability at both of the two impurity regions forming a source or drain and capable of recording 2 bits of data per cell and methods for operating and producing the same.
2. Descriptions of the Related Art
As a nonvolatile semiconductor memory device, there is well known, for example, a so-called metal-oxide-nitride-oxide-semiconductor (MONOS) type memory or a metal-nitride-oxide-semiconductor (MNOS) type wherein, as a charge storing means for storing data, an insulating film formed by stacking a plurality of films is provided. In the MONOS type memory device, an oxide-nitride-oxide(ONO) film and a gate electrode are stacked on a semiconductor forming a transistor channel, for example, a semiconductor substrate, a well, or a silicon on insulator (SOI) layer (hereinafter referred to merely as a xe2x80x9csubstratexe2x80x9d) and source and drain regions having a conductivity type opposite to the substrate are formed in surface regions of the substrate at the two sides of the stacked pattern.
By injecting a charge into an insulating film having a charge storing capability from the substrate side, writing of data is performed. Erasure is achieved by extracting the stored charge to the substrate side or by injecting an opposite polarity charge into the insulating film to cancel the stored charge.
For injection of the charge into the isolation film, there is known a method of using a charge tunneling phenomenon caused inside an insulator and also, for example, so-called channel-hot-electron (CHE) injection and other methods of exciting a charge in energy up to a degree capable of overcoming the insulating barrier of the bottommost oxide film of an ONO film and so on.
Recently, technology taking note of the fact that conventional CHE injection enables injection of a charge into part of a discrete trap area including dispersed charge traps, and enabling storage of 2 bits per memory cell by independently writing binary data to a source side and a drain side of a charge storing means, that is, the stacked insulating film having the charge storing capability, has been reported.
For example, Extended Abstract of the 1999 International Conference on Solid State Device and Materials, Tokyo, 1999, pp. 522-523, considers that it is possible to reliably read 2 bits of data of small amounts of stored charges by the so-called xe2x80x9creverse readxe2x80x9d method by changing the direction of the voltage applied between the source and the drain to write 2 bits of data by CHE injection and, when reading, applying a specified voltage between the source and the drain in a direction reverse to that of the write operation to independently read the 2 bits of data. Further, erasure is performed by forming an inversion layer in a surface region of the source or drain impurity region, causing a high energy charge (hot holes) by avalanche breakdown in the inversion layer, and injecting the hot holes into the charge storing means.
By using this technique, it becomes possible to increase the write speed and greatly reduce the cost per bit.
However, in this memory cell able to store 2 bits of data using conventional CHE injection, the charge storing film (ONO film) is formed on the entire surface of the channel forming region, so the region in which the charge is injected is not limited. Therefore, when the amount of stored charge fluctuates due to the process of the device or nonuniformity of the-bias conditions at the time of operation, this easily can have a delicate effect on the storage characteristics, for example, the change in the threshold voltage. Particularly, when more than the required charge is injected, the change in characteristic at the over-write side becomes a problem since the charge storage region is not limited. Further, since the charge storage region is not limited, there is the disadvantage that the erasure time also becomes long.
Further, a charge trapped in a carrier trap of the charge storing film itself moves much less easily than a charge in a conductive layer, but if the device is held at a high temperature for a long period, so-called xe2x80x9cdilutionxe2x80x9d of storage will occur where there is a certain drift due to heat and the charge retention region expands. In this case as well, in a conventional device structure where the charge storing film is formed uniformly with respect to the entire channel forming region, the relative magnitude of the threshold voltages changes delicately.
There is known that the efficiency of charge injection in conventional CHE injection is a poor one of about 1xc3x9710xe2x88x926. Thus, in a write operation, a large current is required to be passed between the source drain regions in the memory cell. Therefore, there was the problem of the power consumption becoming larger.
On the other hand, in the above conventional memory cell structure, when using a so-called virtual ground (VG) cell array, one type of array with the smallest cell area, while random access makes it possible to enable selection of any one of a plurality of memory cells connected to a single word line, it suffers from the disadvantage that serial access for simultaneously accessing a plurality of memory cells is not possible.
This is due to the fact that in a VG cell array, the source and the drain regions are shared between two adjoining memory cells in the word line direction. This shared relation is repeated in the word line direction. Namely, in a VG cell array, viewed in the word line direction, source and drain regions and channel forming regions having different conductivity types are alternately repeated. Therefore, when determining the voltages in the two source and drain regions in a certain memory cell, to prevent unintentional operation of other memory cells of the same row, the potentials of the other source and drain regions are also inevitably determined. Therefore, leaving aside memory cells for which the intended operation is possible coincidentally under the relative potentials, access to other memory cells basically becomes impossible. Further, conditional serial access where the accessible cells are constantly changing depending on the logic of the stored data is not practical.
For the above reason, when constructing a VG cell array by memory cells of the above conventional structure, it is not possible to freely and independently operate a plurality of memory cells connected to the same word line. As the result, with conventional memory cells, when constructing a VG cell array so as to reduce the cell area, it suffers from the disadvantage of a large number of write operations when writing data to all memory cells connected to one word line and a longer total time required for writing. That is, the superiority in the reduction of the bit cost obtained by use of a VG cell array to reduce the cell area ends up becoming smaller when not using a VG cell array and raising the write efficiency by serial access.
A first object of the present invention is to provide a nonvolatile semiconductor memory device which limits the range of a charge retention region which can store 2 bits of data and is less influenced in characteristics even if an excessive charge is injected and methods for operating and producing the same.
A second object of the present invention is to provide a nonvolatile semiconductor memory device which is raised in efficiency of charge injection, improved in write speed, and reduced in the power consumed by a memory cell in a write operation and methods for operating and producing the same.
A third object of the present invention is to provide a nonvolatile semiconductor memory device which is provided with a means for controlling an ON/OFF state of a channel separate from a normal gate electrode of a memory transistor and which thereby enables serial access of a plurality of memory cells connected with one word line even when using a VG cell array and a method for operating the same.
To achieve the first and second objects, according to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a channel forming region comprised of a semiconductor; a charge storing film including a plurality of stacked dielectric films and having a charge storing capability; two storage portions comprised of regions of the charge storing film overlapping the two ends of the channel forming region; a single layer dielectric film contacting the channel forming region between the storage portions; a control gate electrode contacting the single layer dielectric film; and a memory gate electrode contacting the two storage portions and having portions contacting the storage portions electrically connected with each other.
The channel forming region comprises two outside channel regions facing the memory gate electrode across the storage portion and an inside channel region located between the two outside channel regions and facing the control gate electrode across the single layer dielectric film.
Preferably, the threshold voltages of the three channel regions consisting of the two outside channel regions and the inside channel region are set independently. For example, the threshold voltages of the two outside channel regions are equal.
In this case, preferably, the threshold voltages of the two outside channel regions are lower than that of the inside channel region.
Further, preferably, the channel forming region comprises two outside channel regions facing the memory gate electrode across the storage portion and an inside channel region located between the two outside channel regions and facing the control gate electrode across the single layer dielectric film and wherein a length of the inside channel region defined by the distance between the two outside channel regions is a length enabling carriers to run quasi-ballistically in a channel formed at the time of operation.
The memory gate electrode preferably intersects the control gate electrode in an electrically insulated state and contacts the storage portions at both the outsides of the control gate electrode.
In this case, preferably the device further comprises on the control gate electrode an etching stop layer comprised of a dielectric within etching rate lower than that of a conductive material forming the memory gate electrode.
This is for preventing removal of the dielectric film on the control gate electrode and etching down to the control gate electrode at the time of processing the memory gate electrode.
Preferably, further provision is made of two impurity regions separated from each other from the storage portion sides across the channel forming region and comprised of a semiconductor having a reverse conductivity type to the channel forming region; the two impurity regions are bit lines; the memory gate electrode is a word line for controlling operations including input and output of charges to or from the storage portions; and the control gate electrode is a control line for assisting the operations.
A so-called NOR type memory cell array can be adopted. In this case, the memory cell comprises two impurity regions isolated from each other across the channel forming region from the storage portion sides and comprised of a semiconductor having a conductivity type opposite to the channel forming region; a control transistor having the control gate electrode as a gate and functioning to make two outside channel regions facing the memory gate electrode across the storage portions the source and the drain; and two memory transistors connected in series across the control transistor, each having the memory gate electrode as the gate, and each functioning to make the channel region of the control transistor and one of the two impurity regions as a source or a drain, a plurality of such memory cells being arranged in a matrix to form a memory cell array; each of the two impurity regions being arranged longwise in one direction of the memory cell array and being shared among a plurality of memory cells; and the control gate electrode being arranged in the space separating the two impurity regions parallel to the impurity regions and is shared among the plurality of memory cells.
Further, preferably each of the two impurity regions is isolated from an impurity region of another memory cell adjoining in a direction perpendicular to the longitudinal direction.
A VG type memory cell array can be adopted as a modification of the NOR type. In this case, preferably each of the two impurity regions is shared among memory cells adjoining in a direction perpendicular to the longitudinal direction.
Preferably, memory cells adjoining in one direction are isolated by a dielectric isolation layer.
Preferably, the dielectric isolation layer is arranged in stripes parallel to the memory gate electrodes beneath a space between the memory gate electrodes.
Alternately, the dielectric isolation layer is arranged along the memory gate electrodes beneath a space between the memory gate electrodes and separated on the impurity regions.
Further, preferably the memory gate electrode has sidewalls at the two sides in the width direction, and each of the sidewalls is overlapped with an edge of the dielectric isolation layer across the charge storing film in a region adjoining the storage portion.
In a nonvolatile semiconductor memory device of this configuration, there are two storage portions with charge retention faculties. These two storage portions are separated by a single layer dielectric film not having a charge storing capability. Accordingly, when retaining 2 bits of stored data, the 2 bits of stored data are reliably Bet apart. The reason is that even if excessive charges are injected into the storage portions, due to the existence of the single layer dielectric film not having a charge storing capability between them, the charge injection cannot proceed to more than a certain region, so the regions of distribution of the charges will not interact with each other. Further, even if the retained charges drift when holding the device at a high temperature, since the regions of distribution of the charges do not interact, there will be no dilution of the 2 bits of stored data in this respect either.
Further, providing a resistance difference in the channel forming region raises the efficiency of charge injection in a write or erasure operation.
Furthermore, in a nonvolatile semiconductor memory device according to the first aspect of the present invention, when charges are injected into a storage portion, even if a charge leaks out to the part of the charge storing film at the outside of the memory gate electrode in the channel width direction, a leakage path will not easily form between the channel forming region and the impurity regions due to the effect of the charge. This is because the region of the charge storing film to which the charge leaks rides up on the dielectric isolation layer and, as a result, the effect of the leaked charge on the channel forming region is sufficiently reduced. Further, when forming a dielectric isolation layer, if the memory gate electrode is misaligned in its width direction, there will be a region where the controlling force of the memory gate electrode does not reach and the injected charge is not stored in a write operation. For example, when using a system of injecting a charges of the reverse polarity at an erasure operation, sometimes only a charge having a polarity in a direction turning the channel ON ends up being gradually accumulated with each write operation in the region where the controlling force of the memory gate electrode does not extend. This being the case, a situation arises where the threshold voltage in this region falls sharply and the leakage current increases greatly. In the present invention, to prevent a large increase of leakage current, sidewalls are formed at the two sides of the memory gate electrode in the width direction and sufficient overlap with the charge storing film is realized without an area penalty.
Further, the dielectric isolation layer prevents a channel formed beneath the control gate electrode from extending toward another cell sharing the control gate electrode when turning the control gate electrode ON. When there is a dielectric isolation layer, the region under the control gate of a cell of a not selected word line is electrically insulated. For this reason, even if the control gate turns ON, no channel is formed beneath the control gate of a cell of a not selected word line, over depletion results, and the depleted layer spreads due to the heat equilibrium state. In this state, compared with the state where a channel is formed, the gate capacitance will become much smaller. Accordingly, comparing the case where there is no dielectric isolation layer and a channel is formed beneath the control gate electrode in all cells sharing the gate electrode with the case where a channel is formed in the region beneath a control gate electrode in a cell of a selected word line, but there is a dielectric isolation layer and no channel is formed in the region beneath the control gate electrode in other not selected cells, the capacitance of the control gate in the latter case is smaller. The reduction of capacitance of the control gate contributes to higher speed operation and reduced power consumption of a nonvolatile semiconductor memory device.
From the above, this combination of the dielectric isolation layer and memory gate electrode with sidewalls contributes largely to reduction of the leakage current without an increase of cell area and to a reduction of the gate capacitance and increase of the operating speed. Note that when isolating a dielectric isolation layer on an impurity region, no high resistance portion is formed on the impurity region due to the presence of the dielectric isolation layer.
To achieve the first and second objects, according to a second aspect of the present invention, there is provided a method for operating a nonvolatile semiconductor memory device comprising a channel forming region comprised of a first conductivity type semiconductor, two impurity regions comprised of a second conductivity type semiconductor and separated from each other across the channel forming region, a charge storing film including a plurality of stacked dielectric films and having a charge storing capability, two storage portions comprised of regions of the charge storing film overlapping with two ends of the channel forming region at the two impurity region sides, a single layer dielectric film contacting the channel forming region between the storage portions, a memory gate electrode contacting the storage portions, and a control gate electrode on the single layer dielectric film, the operation including a write operation comprising the steps of: applying a predetermined voltage between the two impurity regions so as to make the impurity region located near the storage portion side to be written the drain and to make the other the source; applying a specified voltage to each of the memory gate electrode and the control gate electrode to form a channel between the two impurity regions; and injecting part of the carriers injecting in the channel into the drain side storage portion.
The step of forming the channel preferably comprises controlling the values of voltages applied to the memory gate electrode and the control gate electrode to form a channel having a channel resistance beneath the two storage portions different from a channel resistance beneath the single layer dielectric film between the two impurity regions.
The step of forming the channel alternatively preferably comprises controlling the values of voltages applied to the memory gate electrode and the control gate electrode to generate a high electric field in a channel region beneath the control gate electrode and in a region of the first conductivity type semiconductor beneath a space between the control gate electrode and the memory gate electrode along the direction of charge injection in the channel.
The operation of reading stored data according to a charge retained by high efficiency CHE injection comprises the steps of: applying a voltage between the two impurity regions so as to make the impurity region at the side of the storage portion retaining the stored data to be read the source and to make the other impurity region the drain; applying specified voltages to each of the memory gate electrode and the control gate electrode; and changing the presence or absence of charge or the difference of amount of charge in the storage portion according to the stored data into the amount of current flowing in the channel forming region or the amount of change of voltage of the impurity regions to read the stored data.
In an erasure operation, it is possible to inject hot carriers due to for example a band-to-band tunnel current or inject a reverse conductivity type high energy charge due to avalanche breakdown. That is, the erasure operation comprises the steps of: applying a voltage for inversion of the impurity region between the impurity region located at the side of the storage portion retaining the stored data to be erased and the memory gate electrode; generating a high energy charge of a polarity opposite to the charge injected at the time of the write operation due to avalanche breakdown or a band-to-band tunneling caused at an inversion layer of the impurity region at the time of applying the voltage; and injecting part of the generated high energy charge into the storage portion retaining the stored data.
Alternatively, the retained charges may be extracted from the entire channel surface or from the impurity region side by using the tunnel phenomenon.
To achieve the first and second objects, according to a third aspect of the present invention, there is provided a method for operating a nonvolatile semiconductor memory device comprising a channel forming region comprised of a first conductivity type semiconductor, two impurity regions comprised of a second conductivity type semiconductor and separated from each other across the channel forming region, a charge storing film including a plurality of stacked dielectric films and having a charge storing capability, two storage portions comprised of regions of the charge storing film overlapping with two ends of the channel forming region at the two impurity region sides, a single layer dielectric film contacting the channel forming region between the storage portions, a memory gate electrode contacting the storage portions, and a control gate electrode on the single layer dielectric film, the operation including a write operation comprising the steps of: applying a voltage between the memory gate electrode and the impurity region located at the storage portion side where the data is to be written in a direction so as to invert the impurity region; generating a high energy charge by avalanche breakdown caused in an inversion layer of the impurity region at the time of applying the voltage; and injecting part of the generated high energy charge into the storage portion of the side where data is to be written.
Preferably, the write operation further comprises a step of changing the potential in the channel forming region beneath the single layer dielectric film according to the potential of the control gate electrode to control the injection position of the high energy charge.
By this, for example, it is possible to limit the charge injection region to part of the impurity region side by applying a voltage of the opposite polarity to the gate electrode to the control gate electrode. Alternatively, it is possible to make the charge injection region the entire area of the intended storage portion by applying a voltage of the same polarity as the memory gate electrode to the control gate electrode.
Preferably, an erasure operation of data stored according to the injected charge comprises the steps of: applying a predetermined voltage between the two impurity regions so as to make the impurity region at the side of the storage portion retaining the stored data to be erased the drain and to make the other impurity region the source; applying specified voltages to each of the memory gate electrode and the control gate electrode to form a channel between the two impurity regions; and injecting part of the carriers having an opposite polarity to the charge injected at the time of the write operation and injecting in the channel into the storage portion retaining the stored data to be erased.
The step of forming the channel preferably comprises a step of controlling the values of voltages applied to the memory gate electrode and the control gate electrode to form a channel having a channel resistance beneath the two storage portions different from a channel resistance beneath the single layer dielectric film between the two impurity regions.
In this way, with the method of operating a nonvolatile semiconductor device according to the second or third aspects of the invention, data is written or erased by so-called type CHE charge injection.
At this time, the channel resistance, for example, becomes higher in the inside channel region beneath the control gate electrode and lower in the two outside channel regions. Accordingly, the voltages applied to these three channel regions become values obtained by proportional distribution of the drain voltage applied between the two impurity regions by the equivalent serial resistance values. In this case, the voltage drop becomes highest in the inside channel region. At this portion, the drain voltage is converted efficiently into energy of the carriers injecting in the channel. In particular, when shortening the control gate length, namely the length of the inside channel region, the carriers move quasi-ballistically in the high electric field region, are accelerated almost without any energy loss, and are emitted to the outside channel regions beneath the storage portion. Accordingly, in the present invention, the ratio of the charges, in the high energy charges emitted, which can overcome the energy barrier of the bottom insulating film in the storage portion of the charge storing film increases and therefore the efficiency of charge injection becomes higher than the conventional case where no resistance difference is given in the channel.
Further, in the present invention, because the charge retention region does not extend to more than the size of the storage portion, even if an over-write occurs, the region of distribution of the threshold voltage will not extend much to the write side. Also, since the charge retention region is limited, over erasure will not easily occur.
Further, at the time of over-writing, the charge sneaks around into the charge storing film at the side of the control gate electrode as well, but there is no need to extract the charge held at this side at the time of erasure since it has almost no effect on the channel. Accordingly, even at over-writing, there is no need for lengthening the erasure time by that amount.
A read operation in the method of operating a nonvolatile semiconductor memory device according to the second and third aspects of the invention comprises reading 2 bits of stored data independently by similar read operations switching the source and drain so that the impurity region of the side to be read becomes the source.
According to a fourth aspect of the preset invention, there is provided a method for operation of a nonvolatile semiconductor memory device comprising memory cells arranged in a matrix to form a memory cell array, each of the memory cells comprising a channel forming region comprised of a first conductivity type semiconductor, two impurity regions comprised of a second conductivity type semiconductor and separated from each other across the channel forming region, a charge storing film including a plurality of stacked dielectric films and having a charge storing capability, two storage portions comprised of regions of the charge storing film overlapping with two ends of the channel forming region at the two impurity region sides, a single layer dielectric film contacting the channel forming region between the storage portions, a memory gate electrode contacting the storage portions, and a control gate electrode on the single layer dielectric film; the memory gate electrode being shared among a plurality of cells in the direction of separation of the impurity regions and comprising a word line; each of the two impurity regions being shared among a plurality of cells in the direction perpendicular to the word line and comprising a bit line; and the control gate electrode being arranged in parallel to the bit line and shared among a plurality of cells in a direction perpendicular to the word line, the method including a read operation comprising a step of applying a voltage of a direction giving a forward bias to the channel forming region to a nonselected word line in a row not including the memory cell to be read.
By application of a voltage in a direction giving a forward bias to the nonselected rows, the potential barrier of the source with respect to the channel becomes higher and an increase in the leakage current due to the so-called DIBL effect is suppressed.
The method of operating a nonvolatile semiconductor memory device according to a fifth aspect of the present invention is for achieving the second object of the present invention and relates to serial operations (write, read, and erasure) of a so-called VG type memory cell array. In a VG type memory cell array, the memory cell array is built by arranging a plurality of memory cells arranged in a matrix. Each memory cell comprises a channel forming region comprised of a first conductivity type semiconductor, two impurity regions comprised of a second conductivity type semiconductor and separated from each other by the channel forming region, a charge storing film including a plurality of stacked dielectric films and having a charge storing capability, two storage portions comprised of regions of the charge storing film overlapping the two ends of the channel forming region at the sides of the two impurity regions, a single layer dielectric film contacting the channel forming region between the storage portions, a memory gate electrode on the storage portions, and a control gate electrode on the single layer dielectric film. The memory gate electrodes in the same row are connected via a word line. Each of the two impurity regions is arranged longwise in the column direction and shared between memory cells adjoining in the row direction. The control gate electrode is arranged long in the column direction and is shared among cells in the same column.
The method for operation comprises the steps of driving the control gate electrode to divide the memory cell array electrically and driving the impurity regions and the word lines to write, read, or erase in parallel a plurality of memory cells in a divided memory cell array.
Preferably, the method comprises the steps of applying at every certain number of control gate electrodes an off voltage for shifting a memory cell to an inactive state where the channel is unable to be turned on; writing, reading, or erasing in parallel memory cells in the active state between memory cells placed in the inactive state due to the division; and repeating the step of dividing the memory cell array and the step of writing, reading, or erasing the memory cells in the active state while shifting the control gate electrodes to which the off voltage is applied in one direction.
In the method of operation according to the fifth aspect of the present investment, the control gate electrode is used as a means for controlling the division of the memory cell array. Namely, when applying an ON voltage to turn the control gate ON, a channel can be formed, while when applying an OFF voltage to turn the control gate OFF, a channel cannot be formed regardless of the presence of application of a drain voltage. If cyclically repeating the OFF state of a control gate for every predetermined number of memory cells in the word line direction, a serial operation becomes possible for active memory cells between the OFF state control gates.
To achieve the third object, according to a sixth aspect of the present invention, there is provided a method for operating a nonvolatile semiconductor memory device comprising a plurality of memory cells arranged in a matrix to form a memory cell array, each of the memory cells comprising a channel forming region comprised of a first conductivity type semiconductor, two impurity regions comprised of a second conductivity type semiconductor and separated from each other across the channel forming region, a charge storing film including a plurality of stacked dielectric films and having a charge storing capability, two storage portions comprised of regions of the charge storing film overlapping with two ends of the channel forming region at the two impurity region sides, a single layer dielectric film contacting the channel forming region between the storage portions, a memory gate electrode contacting the storage portions, and a control gate electrode on the single layer dielectric film; the memory gate electrodes in the same row being connected by a word line; each of the two impurity regions being arranged longwise in the column direction and shared between memory cells adjoining in the row direction; and the control gate electrode being arranged longwise in the column direction and shared between memory cells in the same column, the method for operation including a write operation comprising the steps of: alternately applying a write drain voltage and a reference voltage to the impurity regions in the memory cell array; applying an ON voltage for shifting a channel from an OFF state to a possible ON state to the control gate electrode in combination according to the data to be written; selecting a storage portion located between the control gate electrode applied with the ON voltage and the impurity region applied with the write drain voltage; applying a specified voltage to a word line of a selected row in which the data is to be written to turn the channel on beneath the selected storage portion and injecting part of the carriers injecting in the channel in the selected storage portion; reapplying the write drain voltage and reference voltage to the impurity regions in the memory cell array while switching the locations of application; reapplying the ON voltage to the control gate electrode in combination according to the data to be written; selecting the remaining storage portion different from above storage portion; and reapplying the voltage to the word line to turn the channel on beneath the selected storage portion and injecting part of the carriers injecting in the channel in the selected storage portion.
When writing data to the entire memory cell array using the method of operation according to the sixth aspect, preferably the method comprises the steps of fixing the potential of the impurity regions and in that state successively selecting the word line to which the memory cell to be written with data is connected and repeating the selection of the storage portion and the injection of carriers into the selected storage portion while changing the application of the ON voltage to the control gate electrode according to the data to be written for each selected word line for all word lines in the memory cell array; reapplying the write drain voltage and reference voltage to the impurity regions in the memory cell array while switching the locations of application; and fixing the potential of the impurity regions and in that state successively selecting the word line to which the memory cell to be written with data is connected and repeating the selection of the storage portion and the injection of carriers into the selected storage portion while changing the application of the ON voltage to the control gate electrode according to the data to be written for each selected word line for all word lines in the memory cell array.
Generally, to operate a cell the fastest, it is necessary to minimize the number of charging and discharging cycles of signal or power supply lines. In particular, it is necessary to minimize the number of time-consuming potential changing cycles for charging and discharging. Here, it is believed the common lines take the most time for charging and discharging since the impurity regions have a high resistance and the RC time-constant determined by the resistance R and capacitance C is large.
In the above method for operating a nonvolatile semiconductor memory device according to the sixth aspect of the present invention, both when writing memory cells in the same row and when writing the entire memory cell array comprised of a plurality of rows, the writing of all memory cells ends while raising and lowering the potentials of impurity regions between the high level and low level once. Therefore, the time for a write operation including a change in potential of signals or power supply lines is short.
To achieve the third object, according to a seventh aspect of the present invention, there is provided a method for operating a nonvolatile semiconductor memory device having memory cells arranged in a matrix to form a memory cell array, each memory cell comprising a channel forming region comprised of a first conductivity type semiconductor, two impurity regions comprised of a second conductivity type semiconductor and separated from each other by the channel forming region, a charge storing film including a plurality of stacked dielectric films and having charge storing capability, two storage portions comprised of regions of the charge storing film overlapping with the two ends of the channel forming region, a single layer dielectric film contacting the channel forming region between the storage portions, a memory gate electrode on the storage portions, and a control gate electrode on the single layer dielectric film, wherein the memory gate electrodes in the same row are connected via a word line, each of the two impurity regions is arranged longwise in the column direction and shared between cells adjoining in the row direction, and the control gate electrode is arranged longwise in the column direction and shared between cells in the same column, comprising reading by a first reading step of reading one storage portion of odd-numbered memory cells in the same row in the memory cell array (hereinafter referred to as a xe2x80x9creading step (1)xe2x80x9d), a second reading step of reading the other storage portion of the odd-numbered memory cells included in the same row (hereinafter referred to as a xe2x80x9creading step (2)xe2x80x9d), a third reading step of reading one storage portion of even-numbered memory cells in the same row (hereinafter referred to as a xe2x80x9creading step (3)xe2x80x9d), and a fourth reading step of reading the other storage portion of the even-numbered memory cells in the same row (hereinafter referred to as a xe2x80x9creading step (4)xe2x80x9d).
Preferably, the read operation comprises the steps of resetting to apply a reference voltage to all of the impurity regions and apply an OFF voltage to all of the control gate electrodes; selecting the odd-numbered memory cells or the even-numbered memory cells by alternately applying to the control gate electrodes in the memory cell array an ON voltage for shifting a channel from an OFF state to a possible ON state and an OFF voltage for holding the channel in the OFF state; changing the memory cells selected by switching the application of the ON voltage and the OFF voltage; alternatively applying to the impurity regions in the memory cell array the reference voltage and the read drain voltage so as to select a pair of the storage portions on the two sides of an impurity region to which the reference voltage is applied; and changing the pair of storage portions selected by switching the application of the reference voltage and the read drain voltage.
More preferably, a read operation on a plurality of memory cells in the same row comprises the steps of resetting; selecting a pair of storage portions; performing a first reading operation by selecting a memory cell; performing a second reading operation by changing the memory cell selected; resetting; performing a third reading operation by selecting a memory cell; and performing a fourth reading operation by changing the memory cell selected.
When using this method of operation according to the seventh aspect to read the entire memory cell array, a preferable first method fixes the conditions of application of voltage to the impurity regions and the control gate electrodes and repeatedly performs any of the above reading steps (1), (2), (3), and (4) according to the selection of the impurity regions and control gates on all words in the memory cell array. Next, it changes the voltage application conditions of the control gate electrodes (alternately switching them) and then repeatedly performs any of the above reading steps (1), (2), (3), and (4) able to be performed under the conditions fixing the potentials of the control gate electrodes and impurity regions for all of the rows in the memory cell array. Next, the method changes the voltage application conditions of the impurity regions (alternately switching them) and repeatedly performs any of the above reading steps (1), (2), (3), and (4) able to be performed under the conditions fixing the potentials of the control gate electrodes and impurity regions for all rows in the memory cell array. Next, it changes the voltage application conditions of the control gate electrodes (alternately switching them) and then repeatedly performs any of the above reading steps (1), (2), (3), and (4) able to be performed under the conditions fixing the potentials of the control gate electrodes and impurity regions for all of the rows in the memory cell array.
In this first method, the order of the switching of application of voltage to the impurity regions and the switching of the application of voltage to the control gate electrodes may be reversed. Namely, a preferable second method fixes the conditions of application of voltage to the impurity regions and the control gate electrodes, then repeatedly performs any of the above reading steps (1), (2), (3), and (4) according to the selection of the impurity regions and control gates on all rows in the memory cell array. Next, it changes the voltage application condition of the impurity regions (alternately switching them) and then repeatedly performs any of the above reading steps (1), (2), (3), and (4) able to be performed under the conditions fixing the potentials of the impurity regions and control gate electrodes for all of the rows in the memory cell array.
Next, the method changes the voltage application conditions of the impurity regions (alternately switching them) and repeatedly performs any of the above reading steps (1), (2), (3), and (4) able to be performed under the conditions fixing the potentials of the control gate electrodes and impurity regions for all rows in the memory cell array. Next, it changes the voltage application conditions of the control gate electrodes (alternately switching them) and then repeatedly performs any of the above reading steps (1), (2), (3), and (4) able to be performed under the conditions fixing the potentials of the control gate electrodes and impurity regions for all of the rows in the memory cell array. Next, it changes the voltage application condition of the impurity regions (alternately switching them) and then repeatedly performs any of the above reading steps (1), (2), (3), and (4) able to be performed under the conditions fixing the potentials of the impurity regions and control gate electrodes for all of the rows in the memory cell array.
In the above method for operation of a nonvolatile semiconductor memory device according to the seventh aspect of the present invention, both when reading memory cells in the same row and when reading the entire memory cell array comprised of a plurality of rows, the reading of all memory cells ends while raising and lowering the potentials of impurity regions between the high level and low level once. Therefore, the time for a read operation including a change in potential of signals or power supply lines is short.
To achieve the first and second object, according to an eighth aspect of the present invention, there is provided a method for producing a nonvolatile semiconductor memory device including a memory cell comprising a channel forming region comprised of a first conductivity type semiconductor, two impurity regions comprised of a second conductivity type semiconductor and separated from each other across the channel forming region, a charge storing film including a plurality of stacked dielectric films and having a charge storing capability, two storage portions comprised of regions of the charge storing film overlapping the two ends of the channel forming region at the two impurity region sides, a single layer dielectric film contacting the channel forming region between the storage portions, a memory gate electrode on the storage portions, and a control gate electrode on the single layer dielectric film, the method comprising the steps of forming on the first conductivity type semiconductor a pattern of the single layer dielectric film and the control gate electrode on the dielectric film; forming the charge storing film covering the surface of the pattern and the surface of the first conductivity type semiconductor; forming sidewalls comprised of a conductive material facing the side faces of the pattern across the charge storing film on the portion of the charge storing film forming the storage portion; doping a second conductivity type impurity into the first conductivity type semiconductor outside the sidewalls using the sidewalls and the pattern as masks to form the two impurity regions having a second conductivity type; and forming a conductive film for forming the memory gate electrode together with the sidewalls and processing the conductive film to form the memory gate electrode.
Preferably, the method comprises the steps of doping an impurity for defining the threshold voltage of a part of the channel forming region beneath the control gate electrode into an entire surface region of the first conductivity type semiconductor; forming the pattern; and adding the impurity to a part of the channel forming region around the pattern to adjust the threshold voltage thereof.
In this method, just by adding to a conventional method of manufacture of the memory cell able to store 2 bits a step of forming a stacked pattern of a single layer dielectric film not having a charge storing capability and a control gate electrode, a memory cell having various beneficial effects as mentioned above can be produced.